This invention relates to real-time digital image generation in which the scanline pixels are subdivided into fractional pixels to minimize the "staircase" effect, and more particularly to such image generation in which the fractional pixels within each pixel are nonuniform in size.
Heretofore, the "staircase" effect has been reduced by increasing the pixel clock rate to generate smaller pixel periods with a correspondingly greater scanline position resolution. The maximum reliable clock rate is limited by the separation between adjacent clock pulses. Fast hardware such as ECL-III and other fast logic techniques may be employed to increase the maximum clockrate. The clockrate may be increased until the trailing portion of each clockpulse overlaps with the rising portion of the next pulse causing spurious clocking effects.